Mansionstraat 4 - B-2990 Wuustwezel

Services

  • VHDL design
    • Modular and hierarchical design approach.
    • Optimised coding style for speed or area.
    • Translation of C-code, Matlab or Mathematica models towards VHDL.
    • Focus on readability and re-use.
    • Self-checking testbenches on all design levels.
    • Extensive scripting for compilation automation.
    • Simulation models for ASSP components.
    • ASIC to FPGA conversion.
    • Integration of IP cores.
    • FPGA design from concept to tested HW.
    • Design and simulation of ASIC modules.
  • Feasibility study
    • Preliminary estimation of required logic, suitable FPGA types, speed grades and densities in function of the design specifications.
    • Concept analyse by using Matlab and Mathematica modeling.
  • Documentation
    • Documentation of existing VHDL code.
    • Description of system structure and functionality.
  • Prototyping
    • Design of small digital prototype boards:
      • FPGA and ASIC evaluation boards.
      • Small embedded controller boards.
    • Software development in “C”:
      • Low-level drivers.
      • Test software.
      • Embedded system software.
  • Testing
    • VHDL testbenches.
    • On-site, on-platform debugging of FPGA functionality.
    • Test software in C.
  • Tooling
    • Simulations : Modelsim
    • Modeling : Matlab or Mathematica
    • Fitters : QuartusII, ISE and Libero